Memory control apparatus and method for assigning a cache memory to store clean and dirty data based on a memory in the cache memories

ABSTRACT

A memory control apparatus is interposed between a central processing unit and a memory device to store data includes a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus assigns cache memories to store clean data and dirty data, which is updated data corresponding to the clean data, in accordance with a data identifier, whether a slot number is odd or even, or a usable amount of memory in the cache memories. The memory control apparatus selects a cache memory to store the data so as to almost equalize usage in the plurality of cache memories, thereby controlling the allocation of the cache memories.

[0001] The present application is a continuation of application Ser. No.10/162,638, filed Jun. 6, 2002, which is a continuation of applicationSer. No. 09/370,998, filed Aug. 10, 1999, now U.S. Pat. No. 6,434,666;which is a continuation of application Ser. No. 08/601,358, filed Feb.16, 1996, now U.S. Pat. No. 5,987,569, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The invention relates to an information processing systemincluding a memory device and a memory control apparatus having aplurality of cache memories and, more particularly, to a memory controlapparatus of an information processing system in which a memory deviceuses a Redundant Array of Inexpensive Disks (RAID) technique.

[0003] In a conventional memory control apparatus having a cache memory,in response to a write instruction from a central processing unit,completion of a writing process is reported to the central processingunit when write data has been stored into the cache memory in the memorycontrol apparatus. The storage of the write data into a disk device isexecuted by the memory control apparatus asynchronously with the writeinstruction from the central processing unit. Such a control is called awrite-after control. In the write-after control, when the end of writingprocess is reported to the central processing unit, since data is nottransferred to the disk device, a high-speed response to the centralprocessing unit can be performed.

[0004] In the data stored in the cache memory, the data before it istransferred to the disk device is called dirty data, and the data whichcoincides with the data in the disk device is called clean data. In aninformation processing apparatus for performing the write-after control,dirty data is data which exists only on the cache memory in the memorycontrol apparatus. Therefore, the dirty data cannot be deleted until thetransfer to the disk device is finished.

[0005] Data transfer speed between the cache memory and the disk deviceis slower than data transfer speed between the central processing unitand the cache memory. There is consequently, a case where the cachememory is filled with the dirty data at the time of the write-aftercontrol. Therefore, a memory control apparatus disclosed inJP-A-4-264940 monitors an amount of dirty data in the cache, an inflowamount of write data to the cache memory of each memory device, and anoutflow amount of dirty data due to the write-after process. When thedirty data amount in the cache reaches a certain threshold value(permission amount), a limitation of the allocation of the cache memoryto the write data and a data writing preferential execution to thememory device are executed for the memory device in which (the inflowamount)>(the outflow amount). Due to the above control, a deteriorationin performance of the whole system caused by the cache memory entering afull state is avoided and the distribution of the allocation of thecache memory for every memory device can be properly performed.

[0006] In the write-after process, since the cache memory is volatile,there is a possibility that the dirty data is deleted due to a fault ofa power source of a control apparatus or the like, a fault of a hardwareof the cache memory, or the like. Therefore, in “Evolution of the DASDstorage control” disclosed in IBM SYSTEMS JOURNAL, Vol. 28, No. 2, 1989,a memory control apparatus has therein a cache memory and a non-volatilestorage (NVS) of a small capacity for backup of dirty data, and thedirty data is duplexed and held in the cache memory and non-volatilestorage (NVS), thereby preventing deletion of the dirty data.

[0007] Further, a memory control apparatus having a plurality of cachememories which is backed up by a battery is disclosed in JP-A-5-189314.The memory control apparatus has a cache memory whose power source isdepleted by a battery backup. The cache memory is divided into Nportions and data read out from a memory device by a command from anupper apparatus is stored into an arbitrary one of the N dividedportions of the cache memory. Data which is written into the cachememory by an instruction from the upper apparatus is stored into twoarbitrary ones of the N divided portions of the cache memory. Thus,performance of the data at the time of a fault is improved and adeterioration of the performance can be prevented.

[0008] When using the RAID technique for the disk device as a memorydevice, the memory control apparatus needs to form parity data toguarantee data at the time of the write-after process. Therefore, boththe dirty data (write data) and the clean data (data which is updated bythe write data) need to be held on the cache memory.

[0009] In the memory control apparatus disclosed in JP-A-5-189314 inwhich data is duplexed and stored into a plurality of cache memories,the amount of data which cannot be deleted until the data transfer tothe disk device is completed is largely divided between the depletedcache memories depending on an allocating method of the cache memory forthe clean data. When an amount of dirty data (including the clean datato form parity data) in one cache memory reaches a cache memory capacityor a preset dirty data threshold value (permission amount), even in thecase where there is a usable area in the other cache memory, the dirtydata cannot be duplexed. Thus, a response by the write-after processcannot be performed and the performance deteriorates.

[0010] FIGS. 8(a) and 8(b) show a case where a cache surface (cache forstoring clean data and dirty data as updated data of the clean data) andan NVS surface (cache to store the dirty data) of each of a cache A 80and a cache B 81 of a memory control apparatus are fixedly used.

[0011] When using one of the two cache memories as a cache surface andthe other as an NVS surface, as shown in FIG. 8(a), an amount of dirtydata in the cache A 80 that is used as a cache surface is larger than anamount of dirty data in the cache B 81 that is used as an NVS surface.Thus, as shown in FIG. 8(b), when the cache A 80 which is used as acache surface is filled with the dirty data, in spite of the fact that anew usable area c still remains in the cache B 81, the dirty data cannotbe duplexed. Therefore, the write-after process cannot be performed.

SUMMARY OF THE INVENTION

[0012] An object of the invention relates to an allocation of cachememories and intends to improve the efficiency using or allocating ofcache memory space by controlling a balance of using states of aplurality of cache memories.

[0013] To accomplish the above object, a memory control apparatusaccording to the invention comprises: a channel control unit, interposedbetween a central processing unit and a memory device for storing data,for controlling a data transfer to/from the central processing unit; adrive control unit for controlling data transfer to/from the memorydevice; a plurality of cache memories for temporarily storing data thatis transferred between the central processing unit and the memorydevice; and a cache memory control unit having selecting means forselecting the cache memory to store data which is transferred from thememory device. The selecting device arbitrarily selects a first cachememory which is used as a cache surface and a second cache memory whichis used as an NVS surface from among a plurality of cache memories.There is a case where the cache memory control unit of the memorycontrol apparatus has a memory device for storing control information ofthe memory control apparatus.

[0014] When the data is read out from the memory device, the memorycontrol apparatus transfers the read data to the central processing unitand stores the data in the cache memory. In this instance, a memorycontrol apparatus arbitrarily selects the cache memory, which is used asa cache surface (a cache for storing clean data and dirty data which isupdated data of the clean data) from a plurality of cache memories, andstores the data in the selected cache memory.

[0015] When the data is written into the memory device, on the otherhand, the memory control apparatus stores the write data transferredfrom the central processing unit into the cache memory. In thisinstance, when the data which is updated by the write data has beenstored as clean data in the cache memory, the cache memory is used as acache surface, and clean data and dirty data which is updated data ofthe clean data are stored in the cache surface. The memory controlapparatus arbitrarily selects the cache memory which is used as anon-volatile storage (NVS) surface from a plurality of cache memoriesand stores the dirty data into the cache memory.

[0016] As a specific method for when the memory control apparatusselects the cache memory, there is a method of selecting a cache memoryon the basis of a virtual or physical address or an identifier of datasuch as a sequence number or the like when dividing into managementunits.

[0017] There is another method including the steps of: storingusable/unusable state information of each of the unit memories includedin the cache memory into the control memory of the memory controlapparatus; and calculating the number of usable unit memories of each ofthe cache memories with reference to the usable/unusable stateinformation of each of the unit memories, and wherein the cache memoryis selected by the usable unit memory.

[0018] There is yet another method including the steps of: storingmemory usage amount information for each of the cache memories into thecontrol memory of the memory control apparatus; arbitrarily selectingthe first cache memory and the second cache memory from a plurality ofcache memories on the basis of the memory usage amount information ofeach of the cache memories; and storing dirty data amount informationfor each of the cache memories or clean data amount information to formparity data in the control memory, and wherein the cache memory isselected on the basis of the dirty data amount information of each ofthe cache memories or the clean data amount information to form theparity data.

[0019] According to the invention, when data is read out from the memorydevice, the memory control apparatus selects the cache memory which isused as a cache surface from a plurality of cache memories and storesthe read data as clean data into the selected cache memory. Whenupdating the clean data, the memory control apparatus selects the cachememory which is used as an NVS surface from the plurality of cachememories and stores the write data into each of the cache memories whichare used as a cache surface and an NVS surface. In this instance, theclean data stored in the cache memory that is used as a cache surface isalso held in the cache memory.

[0020] As mentioned above, the memory control apparatus according to theinvention arbitrarily selects the cache memories to be used as a cachesurface and an NVS surface from the plurality of cache memories.Therefore, a deviation of the using states among the plurality of cachememories can be reduced.

[0021] When the memory control apparatus selects the cache memory on thebasis of an address of the data or a sequence number of the data, thedata of a certain group unit having certain characteristics is dividedand allocated into the plurality of cache memories by the address orsequence number of the data. Therefore, expected values of probabilitiesat which the data in the cache memory is updated are averaged among theplurality of cache memories and a cache memory space can be effectivelyused. That is, the probability of the data to be updated differsdepending on the characteristics of the data. Therefore, by allocating agroup of data to the same cache memory, the occurrence of a deviation ofthe dirty data amounts among the plurality of cache memories inaccordance with the data characteristics is prevented, so that whichcache memory is allocated to the divided data is decided by anidentifier of the data.

[0022] When the memory control apparatus selects the cache memory on thebasis of the number of requests for the allocation of the cache memory,the memory control apparatus has means for storing the number ofprocesses by the cache memory selecting process or the number of blocksallocated to the control memory. The memory control apparatus selectsthe cache memory on the basis of the number of processing times or thenumber of blocks. Therefore, since the probability values at which thedata in the cache memory is updated are averaged among the plurality ofcache memories, the cache memory space can be effectively used.

[0023] Further, when the memory control apparatus selects the cachememory on the basis of the cache memory using state, the memory controlapparatus has means for storing the using state information of each ofthe plurality of cache memories in the control memory. The memorycontrol apparatus selects which cache memory is allocated in accordancewith the using state of the cache memory. According to the above controlmethod, by averaging the present using states of the cache memories, thecache memory space is effectively used.

[0024] On the other hand, the cache memory in the memory controlapparatus of the invention includes a plurality of unit memories and canclose every unit memory. When a certain unit memory is closed, the cachememory including the closed unit memory is called a degenerate state.When there is a cache memory in the degenerate state, a balance of thecapacities among the plurality of cache memories is divided. Therefore,it is necessary to control the memory allocation in consideration of acapacity ratio of the cache memory. For this purpose, the memory controlapparatus has means for storing the closed state information of eachunit memory as a component element of the plurality of cache memories,calculating the capacity of each cache memory by the closed stateinformation, and selecting the cache memory to be allocated inaccordance with a capacity ratio. In this instance, the above method canbe also commonly used.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 shows an information processing system according to anembodiment of the invention;

[0026]FIG. 2 shows detailed contents of a cache using state information;

[0027]FIG. 3 shows detailed contents of cache construction stateinformation;

[0028]FIG. 4 shows an example of a selecting process of a cache memoryof a cache surface;

[0029]FIG. 5 shows an example of the selecting process of the cachememory of the cache surface;

[0030]FIG. 6 shows an example of the selecting process of the cachesurface;

[0031]FIG. 7 shows an example of the selecting process of the cachesurface; and

[0032]FIG. 8 is an explanatory diagram of a prior art construction ofthe subject matter of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] An embodiment of the invention will now be described hereinbelowwith reference to the drawings.

[0034]FIG. 1 shows an information processing system according to anembodiment of the invention. The information processing system has acentral processing unit (CPU 1), a memory device 2, and a memory controlapparatus 3 connected to the processing unit 1 and memory device 2.

[0035] The memory control apparatus 3 is connected to the processingunit 1 through a channel control 31 and is connected to the memorydevice 2 through a drive control 32. Further, the memory controlapparatus 3 includes therein: non-volatile cache memories A 33 and B 34which are made nonvolatile by a battery power source; a space allocationunit 35; a drive control unit 36; a cache control unit 37; aconstruction control unit 38; and a control memory 39.

[0036] A construction of the memory device 2 and an outline of a flow ofdata will now be described. The memory device 2 includes a disk arrayhaving a plurality of disk devices 21. In the disk array, data 22 isdivided and divided data 221 is stored into the other different diskdevices 21, respectively. Data (parity data) 222 to guarantee the datais formed by the divided data 221 and is stored into the disk device 21different from the disk device in which the data 221 was stored.

[0037] In the embodiment, the divided data 221 is managed on a slot unitbasis. The “slot” includes a plurality of records and is a unit which ismanaged by a unique number called a slot number. A state in which thedata corresponding to a read request and a write request issued from theprocessing unit 1 already exist in the cache memory A 33 or B 34 isreferred to as a read hit and a write hit, respectively. On thecontrary, a state in which the requested data does not exist in thecache memory is referred to as a read miss and a write miss,respectively. In the cache memory, data which coincides with the data inthe memory device 2 is called clean data. In the cache memory, updatedor modified data which is not stored in the memory device 2 but has beenstored in only the cache memory is called dirty data.

[0038] When the read request for the data 22 in the memory device 2 isissued from the processing unit 1, the data is read out by each diskcontrol unit and, after that, the data 22 is stored in the cache memoryA 33 or B 34.

[0039] When the write request for the memory device 2 is issued from theprocessing unit 1, the data to be updated is read out from the memorydevice 2 into the cache memory at the time of the write miss. When theupdated data is written into the cache memory, the memory controlapparatus 3 returns a response indicative of the end of the writingprocess to the processing unit (write-after control). In the writingprocess, the data written in the cache memory becomes dirty data. Thedirty data is duplexed and stored in the cache memories A 33 and B 34.In this instance, the clean data before updating which was read out fromthe memory device 2 is held as it is in the cache memory.

[0040] The process of writing the dirty data into the memory device 2 isexecuted asynchronously with the write request from the processing unit1. New parity data is formed by the dirty data and clean data in thecache memory. The dirty data and the new parity data are written intothe memory device 2. When the writing process is finished, the targetdata of the writing process does not need to be duplexed and held asdirty data in the cache memories. This data, accordingly, is held asclean data in either one of the two cache memories. The data can be alsodeleted from the chosen cache memory.

[0041] As mentioned above, the cache memory which stores the clean dataand the dirty data, in which the clean data was updated, is called acache surface and the cache memory which stores the other one of theduplexed dirty data is called an NVS surface.

[0042] Control of the memory control apparatus which is used in theinvention will now be described. The cache memory A 33 is constructed byn unit cache memories (A-1, A-2, . . . , A-n) 331 which can beindividually closed. A state of the cache memory including the closedcache memory unit is referred to as a degenerate state. A state of thecache memory wherein all of the unit cache memory units 331 included inthe cache memory are closed is referred to as a closed state. The sameshall also be similarly applied to the cache memory B 34 and unit cachememories 341.

[0043] The cache control unit 37 has space allocation means 371 forallocating the cache memory to store data when the data is stored intothe cache memory in association with the reading/writing process fromthe processing unit 1.

[0044] A construction control unit 38 manages a normal/closed state ofeach of the cache memory units 331 and 341 and anormal/degenerate/closed state of each of the cache memories 33 and 34,and holds cache construction state information 392 in control memory 39.The cache control unit 37 manages using states of the cache memories 33and 34 and holds cache using state information 391 in the control memory39.

[0045]FIGS. 2 and 3 show the details of the cache using stateinformation 391 and cache construction state information 392. Usagestate information 3911 of the cache memory A and usage state information3912 of the cache memory B are included in the cache using stateinformation 391. Total capacities 39111 and 39121, total use amounts39112 and 39122, dirty data amounts 39113 and 39123, and usable memorycapacities 39114 and 39124 are recorded in the using state information3911 and 3912, respectively. The total capacity is a capacity of theinstalled cache memory. The usable memory capacity is a normal totalcapacity of the unit cache memory. Cache memory A construction stateinformation 3921 and cache memory B construction state information 3922are included in the cache construction state information 392. Cachememory usable/unusable information 39211 and 39221 and unit cache memoryusable/unusable information 39212 and 39222 are held in the constructionstate information 3921 and 3922, respectively. Further, the number ofexecutions of the selecting process of the cache memory of the cachesurface, namely, the number of executions of the allocation of thememory for the clean data is stored into the cache memory of the cachesurface by the cache control unit 37. The cache control unit 37 usesthat information when the cache memories are allocated.

[0046] An example of a process for selecting the cache memory which isused as a cache surface from the cache memory A 33 or B 34 whenallocating the cache memories will now be described. In the embodiment,since only two cache memories are provided, the selecting process of theNVS surface is unnecessary.

[0047] When the read request is issued from the processing unit 1 to thememory device 2, the read data is read out from the disk device and thenthe data 22 is stored in the cache memory selected as a cache surface bythe cache control unit 37.

[0048] When the write request is issued from the processing unit 1 tothe memory device 2, in case of the write miss, the cache memory whichis used as a cache surface is selected by the cache control unit 37. Thememory control apparatus 3 stores the updating target data which wasread out from the memory device 2 into the cache memory of the cachesurface, and writes the updated data into the cache memory serving as acache surface and the other cache memory serving as an NVS surface. Incase of the write hit, the dirty data, which is updated data for theclean data is stored in the cache memory of the cache surface in whichthe clean data has been stored with the other cache memory, saved as anNVS surface. In this instance, the clean data is held as it is in thecache memory of the cache surface.

[0049] An example of the process for selecting the cache memory that isused as a cache surface will now be described with reference to aflowchart.

[0050]FIG. 4 shows an example of the process of selecting the cachememory which is used as a cache surface. The cache control unit 37refers to the slot number of the data which is stored in the cachememory (step 400). A check is made to see if the slot number is an evennumber or an odd number (step 410). When the slot number is an evennumber, the cache memory A 33 is selected as a cache memory which isused as a cache surface (step 420). When the slot number is an oddnumber, the cache memory B is selected as a cache memory which is usedas a cache surface (step 430). The allocating process of the cachememories then is executed (step 440). In the example, although the aboveselection ? determination has been made on the basis of whether the slotnumber is an even number or an odd number, so long as any deviation ofdata characteristics is small, it is also possible to distribute thecache surfaces to every slot number and to select therefrom.

[0051]FIG. 5 shows another example of the process of cache memoryselecting process of the cache memory which is used as a cache surface.The cache control unit 37 refers to the cache memory A dirty data amount39113 in the control memory 39 and the cache memory B dirty data amount39123. The dirty data amounts 39113 and 39123 are compared (step 510).The cache memory of a smaller dirty data amount is selected as a cachememory which is used as a cache surface (steps 520, 530). The allocationof the cache memories is performed (step 540).

[0052]FIG. 6 shows still another example of the cache memory selectingprocess of the cache surface. In step 600, the cache control unit 37refers to a counter 393. In step 610, a determination is made to see ifa counter value of the counter 393 is an even number or an odd number,and on the basis of the determination result, the cache surface cachememory A or B is selected (steps 620, 630). The cache memories areallocated in step 640.

[0053]FIG. 7 shows another example of the cache memory selecting processof the cache surface. The cache control unit 37 refers to the cacheconstruction state information 392 (step 700). The usable memorycapacities 39114 and 39124 of the cache memories are calculated,respectively (step 710) and are recorded in the cache using stateinformation 391. Subsequently, a usable memory capacity ratio of everycache memory surface is calculated (step 720). It is now assumed thatthe capacity ratio (cache memory A: cache memory B) is equal to N:M. Instep 730, the slot number is referred to in a manner similar to theselecting process shown in FIG. 4. A remainder when the slot number isdivided by (N+M) is obtained (step 740). When the remainder is equal toor less than N, the cache memory A is selected as a cache surface (step750). In the other cases, the cache memory B is selected as a cachesurface (step 760). In step 770, the cache memories are allocated. Inthe example, although the selection of the cache surface by the slotnumber has been shown, the selecting process by the counter value shownin FIG. 6 can also be used in steps 730 to 750.

[0054] The example of the selecting process of the cache memory of thecache surface has been shown above. In the embodiment, since only twocache memories are provided, the selecting process of the NVS surface isunnecessary. When providing N cache memories, however, the selectingprocess is also needed with respect to the selecting process of the NVSsurface. In such a case, it will be obviously understood that theselecting process of the cache memory as a cache surface can be applied.

[0055] The memory control apparatus according to the invention canarbitrarily select the cache memory which is used as a cache surface oran NVS surface from among a plurality of cache memories. Therefore, theusing states of the cache memories can be preferably balanced and thereis an effect such that the using efficiency of the space of the cachememory is improved.

What is claimed is:
 1. A memory control apparatus, in a RAID structurewhich is interposed between a central processing unit and a memorydevice for storing data, having a cache memory for temporarily storingdata of said memory device, and for transferring data between saidcentral processing unit and said memory device, said memory controlapparatus comprising: a control unit for controlling said cache memoryand for assigning a region of said cache memory for storing clean data,and another region of said cache memory for storing said dirty datawhich is updated data corresponding to the clean data, wherein saidcontrol unit assigns the region of said cache memory in accordance withat least one of data identifier, a data slot number, or a usable memoryamount in a cache memory when said control unit stores data in saidcache memory.
 2. A memory control apparatus, which is interposed betweena central processing unit and a memory device for storing data, having acache memory for temporarily storing data of said memory device, fortransferring data between said central processing unit and said memorydevice, said memory control apparatus comprising: a control unit forcontrolling said cache memory and for assigning a region of said cachememory for storing clean data, and another region of said cache memoryfor storing said dirty data which is updated data corresponding to theclean data; and means for storing cache using state information of eachregion of said cache memory, wherein the region of said cache memory forstoring is assigned in accordance with a comparison between said cacheusing state information of each region of said cache memory, when saidcontrol unit assigns a region of said cache memory for storing saidclean data and a region of said cache memory for storing said dirtydata.
 3. A memory control apparatus, which is interposed between acentral processing unit and a memory device for storing data, having aplurality of cache memories for temporarily storing data of said memorydevice, and for transferring data between said central processing unitand said memory device, wherein each of said plurality of cache memoriesincludes at least one region, said memory control apparatus comprising:means for storing usable/unusable information for each region of eachcache memory; and a control unit for controlling said plurality of cachememories and for assigning a region of a cache memory for storing cleandata, and another region of said cache memory for storing said dirtydata, which is updated data concerned with said clean data, inaccordance with said usable/unusable information, wherein said controlunit assigns a region of a cache memory to write-in, when write-in tothe cache memory is to occur.
 4. In a memory control apparatus, which isinterposed between a central processing unit and a memory device forstoring data, having a cache memory for temporarily storing data of saidmemory device, for transferring data between said central processingunit and said memory device, a cache control method, responsive to adata write request from said central processing unit, comprising thesteps of: judging whether said write request is a write hit, and whensaid write request is a write hit, storing dirty data which is updateddata concerned with clean data into a region of said cache memory andstoring clean data into another region of said cache memory; when saidwrite request is not a write hit, reading cache using state informationfrom means for storing cache using state information indicating usingstate for each region of said cache memory, and comparing said cacheusing state information of each of region of said cache memory; and inresponse to said reading and comparing step, assigning a region of saidcache memory for writing said clean data and a region of said cachememory for writing said dirty data.
 5. In a memory control apparatus,which is interposed between a central processing unit and a memorydevice for storing data, having a cache memory for temporarily storingdata of said memory device, for transferring data between said centralprocessing unit and said memory device, a cache control method,responsive to a data write request from said central processing unit,comprising the steps of: determining whether said write request is awrite hit, and when said write request is a write hit, storing dirtydata which is updated data concerned with clean data into a region ofsaid cache memory and storing into another region of said cache memorysaid clean data; and when said write request is not a write hit,assigning a region of said cache memory for writing said clean data andanother region of said cache memory for writing said dirty data inaccordance with either one of a slot number to which an updating objectnumber is stored or an identifier of data, wherein said control unitassigns a region of said cache memory to write-in, when write-in to thecache memory is to occur.